The present invention pertains to a process for the manufacture of integrated devices with gate oxide protection from damage due to the manufacturing process, and to a protection structure therefor. In particular, the present invention relates to a process for the manufacture of integrated devices comprising gate regions of conductive material, electrically insulated with respect to the substrate by an insulating layer (gate oxide).
During the manufacture of integrated devices, a number of technological steps are present (such as, reactive ion-etching (RIE) or plasma deposition and/or etching) which induce the charging of certain layers of the wafer being processed, and specifically of the most exposed layer. When the most exposed layer is a conductor layer (such as defining polycrystalline silicon or metal lines), the voltage is transferred along the entire conductive line, and the system tends to discharge through the weakest point, usually represented by the gate oxide region. This situation is, however, undesirable in that it jeopardizes the reliability of the final device.
Proposed solutions to the foregoing include:
reducing the xe2x80x9cantenna ratioxe2x80x9d, defined by the ratio between the area of the conductive path and the area of the gate oxide region. In this way, the total capacity of the conductor layer that discharges through the gate oxide region is decreased, and thus the amount of charge present, given the same voltage, decreases;
inserting along the interconnections suitable N+/substrate diodes or P+/N well diodes which limit the maximum voltage that may be reached by the conductor layer and, if forward biased, prevent the conductor layer from being charged with negative voltage.
The problem existing in the manufacture of protection diodes normally inserted in integrated devices consists in the fact that the range of allowed voltages (for which there is no protection) is too wide as compared with current requirements, and they are limited by the diode breakdown voltage, typically higher than 10 V. On the other hand, the presence of voltages higher than 10 V on gate oxide regions having a thickness of 12 nm corresponds to the application of electric fields of over 8 MV/cm. In the case of gate oxide layers having a thickness of 7 nm, there are electric fields even greater than 14 MV/cm. These voltages are much higher than normal operating conditions and are even higher than the values at which the Fowler-Nordheim tunnel effect conduction mechanisms start, which may lead to degradation of the oxide regions. In practice, with the thicknesses currently envisaged, traditional diodes are not able to intervene before voltages dangerous for the oxide layers are set up, and hence do not provide an effective protection against damages to the gate oxide layers.
The invention provides a protective structure that prevents damages to the gate oxide layer during the process of manufacturing integrated devices.
According to the invention, a process for the manufacture of integrated devices with gate oxide protection from damages due to the manufacturing process and a protective structure is provided.
Zener diodes, the breakdown voltage of which is approximately 5 V, are inserted on the interconnection lines connected to gate regions, instead of the N+/substrate diodes or P+/N well diodes. The insertion of zener diodes reduces the range of voltages applied to the gate oxide regions without the protection structure intervening. This is particularly advantageous in advanced-technology devices, in which the thickness of the gate oxide may be 12 nm (0.5 xcexcm technology), 7 nm (0.35 xcexcm technology), or 5 nm (0.25 xcexcm technology). The operation of the devices is not affected in that, with such advanced technologies, the operating voltage is scaled down, and is at most 3.3 V with a +10% margin. The value of the breakdown voltage guaranteed by zener diodes is hence more than adequate.
In case of transistors and high-voltage interconnections, which must handle higher voltages (such as those required for the operation of devices comprising non-volatile memories), it is possible to arrange a number of zener diodes in series so as to increase the total breakdown voltage.